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Nitin K
@vnith1
VLSI and FPGA Engineer: RTL to GDS, RTL Design, DSP, RISCV
India
Inglés, Hindi, Kannada
Sobre mí
I am an IIT M.Tech graduate in VLSI with 10+ years of experience in VLSI design, FPGA development, RTL implementation and semiconductor workflows. Skilled in Verilog/SystemVerilog, FPGA, DSP, RISC-V, AI/ML hardware acceleration, RTL-to-GDS flow, Python/TCL scripting and EDA tools commercial tools and open source tools. I provide support for RTL coding, FPGA implementation, debugging, simulation, DSP architectures, IEEE projects, research guidance and implementation-oriented semiconductor solutions.
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Nitin K
desconectado •
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Sistemas integrados e IoT
I will verilog systemverilog rtl fpga and asic design
