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Savindra
@savindra_fpga
FPGA Digital Design Engineer with Verilog, Vivado
Sri Lanka
Inglés, Cingalés
Sobre mí
I am an Electrical and Electronic Engineering undergraduate specializing in FPGA-based digital design and Verilog HDL. My experience includes developing high-performance hardware in Xilinx Vivado, ranging from 32-bit ALUs and nonlinear system models like the Van der Pol oscillator to hardware accelerators for Sobel edge detection. Proficient in the full RTL design cycle—including digital architecture, testbench development, and image processing modules—I focus on delivering clean, fully simulated, and well-documented hardware solutions.
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Savindra
desconectado •
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Sistemas integrados e IoT
I will create verilog rtl designs and testbenches for fpga systems
