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Osama
@osamamanzoor784
Pakistán
Inglés, Urdu, Pashto
Sobre mí
FPGA and RTL Design Engineer with hands-on experience in Xilinx Zynq RFSoCs, RISC-V processor design, and SystemVerilog verification. I've built multicycle and pipelined processors from scratch, worked with RF Data Converters for S-band signal processing, and verified designs using UVM, QuestaSim and Cadence. Currently a Research Affiliate at GIST University, South Korea. I work with clients who need serious hardware engineering done right.
Habilidades
Osama
desconectado •
Revisa mis servicios
Programación y tecnología
I will develop and verify rtl designs using verilog, systemverilog and uvm
Sistemas integrados e IoT
I will design fpga systems using vivado or quartus via verilog systemverilog
