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Aariz
@miraarizahmed
Physical Verification Engineer
India
Inglés
Sobre mí
Hi! I’m a Physical Verification Engineer specializing in SoC/GPU designs. I offer DRC, LVS, ERC, Antenna, and PERC verification using industry-standard EDA tools. I can run PV flows, debug layout violations, and support signoff closure.
Experienced in advanced nodes and full-chip verification. I deliver accurate results, fast turnaround, and clear communication.
Need help with physical verification, layout debugging, or signoff? Let’s work together!
Habilidades
Aariz
desconectado •
Tiempo medio de respuesta: 39 horas
Revisa mis servicios
Placas de circuito impreso (PCB)
I will clean all your block drc lvs ant perc violations using innovus and calibre
Experiencia laboral
Physical Verification Engineer
Company • Tiempo completo
Jan 2025 - Present • 1 yr 4 mos
Physical Verification Engineer with hands-on experience across advanced nodes (3nm, 2nm, 4nm) in TSMC and Samsung foundries, working on high-performance SoC and droplet-based designs. Led block-level physical verification and integration for 10+ blocks in a 3nm SoC project, driving designs from post-route stages to metal tapeout and achieving signoff readiness in collaboration with cross-functional teams. Performed full-suite verification including DRC, LVS, ERC, Antenna, PERC, and DFM checks using Calibre and Innovus. Resolved 20,000+ DRC violations and 3,000+ metal shorts under tight tapeout schedules, ensuring clean and reliable closure. Contributed to 2nm test chip verification, handling DRC, LVS, ANT, and DFM checks, and improving closure efficiency through density optimization and TCL-based automation. Owned physical verification for a 4nm subsystem, ensuring hierarchical signoff readiness and physical convergence. Debugged complex LVS issues (shorts, mismatches, connectivity errors) and supported full-chip integration. Developed TCL automation scripts to reduce manual effort, fix common layout issues (dangling nets, PG via spacing, density violations), and improve overall verification efficiency. Collaborated with CAD, design, and integration teams to optimize verification flows, reduce runtime, and enable successful high-quality tapeouts.
