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karthik_kotebag

Karthik Kotebag

@karthik_kotebag

FPGA RTL Designer, 9 years in industy, Architecture to Validation

Reino Unido
Inglés
Parte de la información aparece en idioma inglés.
Sobre mí
I am an FPGA/RTL Design Engineer with nearly 9 years of experience in FPGA design, IP development, post-silicon validation, and RTL implementation on Intel (Altera) and Xilinx platforms. My expertise includes Ethernet, Automotive Ethernet, MACsec, cryptographic accelerators, and PCIe. I can help with FPGA RTL design (Verilog/SystemVerilog/VHDL), debugging, protocol implementation, testbench development, simulation, timing analysis, design reviews, and technical documentation. I am committed to delivering high-quality solutions, clear documentation, and on-time delivery for your projects.... Lee más

Habilidades

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karthik_kotebag
Karthik Kotebag
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Revisa mis servicios

Sistemas integrados e IoT
I will be your fpga designer, rtl architect, and debugger
DeUSD 10 / proyectoMás información

Experiencia laboral

Intel

FPGA Hardware Engineer

Intel • Tiempo completo

Jun 2021 - Jun 2026 • 5 yrs

In Intel/Altera, I have worked on the development and post-silicon validation of high-speed FPGA and ASIC IPs, including PCIe Switch, MACsec, Serial Lite, PCIe Gen6, and Cryptographic Accelerator IPs. My experience includes RTL design, architecture definition, SystemVerilog implementation, and Validation Soft IP (VSIP) development. I have developed configurable Ethernet and PCIe traffic generators/checkers, performed hardware bring-up, protocol debugging, and collaborated with cross-functional teams to resolve complex design issues. I also created validation frameworks, customer example designs, and protocol-level test content for PCIe and cryptographic IPs.