Haseeb

@haseebumer1

RTL and FPGA Design: RISC V, AI Driven, and IoT Ready Solutions

Pakistán

Inglés, Urdu, Punjabí

Parte de la información aparece en idioma inglés.

Sobre mí

🚀 I'm Haseeb — a Digital Design Engineer specializing in RTL design, FPGA development (VHDL/SystemVerilog), and custom RISC-V cores. I create fast, scalable, and synthesis-ready hardware for Xilinx, Intel & Lattice FPGAs using Vivado, Quartus & ModelSim. I also design AI-powered and IoT-enabled embedded systems, bridging hardware with intelligent, connected solutions. Let’s bring your ideas to life — with precision, performance, and innovation!... Lee más

Habilidades