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Haseeb U
@haseeb_u4
Pakistán
Inglés, Urdu
Sobre mí
🔧 I’m Haseeb, a hardware design engineer with expertise in RTL design, VHDL, SystemVerilog, FPGA development, and RISC-V architecture. I work with Xilinx, Intel, and Lattice FPGAs using tools like Vivado, Quartus, and ModelSim. I deliver synthesis-ready RTL, custom IP cores, and simulation testbenches. Whether you need FPGA prototyping, HDL optimization, or RISC-V customization, I’m here to help. Let’s build efficient and scalable digital systems!
Habilidades
Haseeb U
desconectado •
Tiempo medio de respuesta: 1 hora
Revisa mis servicios
Sistemas integrados e IoT
I will design rtl, verilog, systemverilog modules for fpga and asic digital desi
Sistemas integrados e IoT
I will do rtl verification and uvm testbench development for fpga and asic
