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Digital Design Engineer with 2+ years of experience in Digital System Design and Computer Architecture in the semiconductor industry. Skilled in SystemVerilog RTL design, verification test planning and RTL debugging. Experienced in developing testbenches and working with UART and AMBA AXI protocols.
Hands-on experience in designing and verifying single-cycle and pipelined processors, including 16-bit and 32-bit RISC processors using Vivado.
Skills:
SystemVerilog, Verilog, Python, C, Bash, Makefile.
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Faisal
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Sistemas integrados e IoT
I will design, debug, and optimize riscv digital systems using systemverilog and c
Redacción de currículums
I will optimize, rewrite and revamp your linkedin profile professionally
