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Elieo
@elieo_oye
Verilog VHDL Simulation for FPGA, Debug and Verify
Reino Unido
Inglés
Sobre mí
Hi!
I’m Elieo, an FPGA & Embedded Hardware Engineer with 5+ years of experience.
I work on FPGA simulation, RISC-V systems, debugging, and hardware acceleration for AI and DSP applications.
I deliver verified, timing-optimized designs, high-performance FPGA architectures, and reconfigurable hardware solutions.
I use Verilog, VHDL, Vivado, Quartus, ModelSim, and Vitis.
Delivery includes RTL code, simulation files, testbenches, synthesis reports, and deployment-ready documentation for real hardware projects.
Thank you!
Habilidades
Elieo
desconectado •
Revisa mis servicios
Sistemas integrados e IoT
I will do fpga simulation testbench verification using verilog vhdl
Sistemas integrados e IoT
I will do fpga projects on zynq and virtex soc using xilinx vivado and vitis sdk
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