d
denyrand

denny

@denyrand

Engineer

Pakistán
Inglés
Parte de la información aparece en idioma inglés.
Sobre mí
I have strong expertise in digital design verification using UVM, Verilog, and SystemVerilog. I specialize in building robust testbenches, developing functional coverage, and debugging complex RTL designs. I have hands-on experience with industry-standard tools such as Cadence verification environments and Xilinx Vivado. My background in digital logic design enables me to deliver reliable, efficient, and high-quality verification solutions. I help clients ensure first-time-right silicon through thorough and scalable verification methodologies.... Lee más

Habilidades

d
denyrand
denny
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Revisa mis servicios

Programación y tecnología
I will design solar wind hybrid systems in system advisor model sam
Programación y tecnología
I will do digital logic design, verilog, systemverilog, uvm, and fpga design

Experiencia laboral

Employee of the Year

SemiEdge • Tiempo parcial

Jan 2020 - Present6 yrs 4 mos

FPGA Desgn Engineer at SemiEdge