c
carddesignautom

Joel Reynolds

@carddesignautom

FPGA Design Engineer VHDL, SystemVerilog, Xilinx Zynq, RTL, DSP Embedded System

Reino Unido
Inglés, Español, Alemán
Parte de la información aparece en idioma inglés.
Sobre mí
I am an FPGA and Embedded Systems Engineer specializing in RTL design, VHDL, Verilog, SystemVerilog, and AMD/Xilinx Vivado. I develop high-performance FPGA and ASIC solutions for Xilinx Zynq and UltraScale+ platforms, including DSP48E2, MMCM, PLL, AXI4, PCIe, Ethernet, DDR, and PetaLinux integration. My expertise covers DSP, FSM design, hardware verification, timing closure, HIL, synthesis, and optimized embedded hardware for industrial, AI, robotics, communications, and automation applications.... Lee más

Habilidades

c
carddesignautom
Joel Reynolds
desconectado • 

Revisa mis servicios

Sistemas integrados e IoT
I will design fpga rtl vhdl systemverilog dsp xilinx vivado zynq hil embedded hardware
Sistemas integrados e IoT
I will debug esp32 esp idf firmware mbedtls freertos, iot system pcb hardware and nrf52

Experiencia laboral

Kwork

FPGA & Embedded Systems Engineer

Kwork • Freelance

Nov 2020 - Present5 yrs 9 mos

Designed and developed FPGA and embedded hardware solutions for industrial automation, telecommunications, AI, robotics, and high-speed digital systems. Created synthesizable RTL using VHDL, Verilog, and SystemVerilog for AMD/Xilinx FPGA platforms, including Zynq and UltraScale+ devices. Developed digital signal processing (DSP) architectures using DSP48E2 slices, implemented AXI4/AXI4-Lite interfaces, integrated DDR memory, PCIe, Ethernet, UART, SPI, and I²C peripherals, and optimized clocking with MMCM and PLL resources. Performed RTL simulation, logic synthesis, timing closure, hardware verification, FPGA debugging with Vivado ILA, and hardware-in-the-loop (HIL) validation. Built Embedded Linux and PetaLinux solutions, generated production-ready bitstreams, and collaborated with multidisciplinary engineering teams to deliver reliable, high-performance embedded hardware.