I’m an FPGA/RTL Engineer with hands-on experience delivering digital hardware for 5G NR (High/Low PHY) and RISC-V–based accelerators. I’ve worked in industry roles across RTL design (VHDL/Verilog/SystemVerilog), verification/simulation, static timing analysis (STA), SoC/IP integration, and system/board bring-up. I help clients build reliable, high-performance hardware modules—clean, well-documented, and verified—with strong focus on correctness, timing closure, and real-world integration.
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